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Memory Pig
- The ideal structured ASIC for memory-loaded designs
- Between 1.0 and 4.5Mb of memory
- Memory-to-logic ratio of over 500%
System Slice
- The SoC platform gate array of choice
- Up to 1.8M gates
- Up to 2.6Mb memory
- Useful PLL and DLL macros
Move to 0.18-micron processing with Chip Express and youll realize top-notch performance for your advanced design with minimal NRE and dramatically reduced mask costs.
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Get started now
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Download CX5000 design libraries now. Find out more about CX5000 structured ASICs and how Chip Express can help you slash the costs and remove the risks associated with standard cell orders.
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CX50552
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546
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4,548 |
1,105 |
| CX50422 |
422 |
3,052 |
915 |
| CX50252 |
250 |
1,952 |
742 |
| CX50122 |
117 |
1,104 |
551 |
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CX51761 |
1,755 |
2,568 |
1,089 |
| CX51191 |
1,192 |
1,792 |
889 |
| CX50841 |
841 |
1,300 |
773 |
| CX50561 |
555 |
880 |
647 |
| CX50331 |
334 |
532 |
505 |
| CX50211 |
211 |
360 |
410 |
| CX50101 |
95 |
168 |
284 |
| CX50041 |
44 |
64 |
189 |
2003 Copyright Chip Express. All Rights reserved.
Chip Express Logo is a registered trademark and
Memory Pig is a trademark of Chip Express, Inc.
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